This invention relates to the manufacture of integrated circuits. More particularly, the invention relates to improving the alignment of images between the various layers applied to the integrated circuits.
The manufacture of integrated circuits, such as semiconductor devices, may generally be characterized as a series of photolithography steps, where in each step a photoresist layer is applied to a substrate, images are transferred to the photoresist layer as by passing a light beam through a projection mask, the photoresist layer is developed, portions of the photoresist layer are thereby removed, and the underlying layers are processed, such as by an etching step.
It is desirable to align the various images of each layer one to another. To this end, alignment features are typically formed, such as by etching an alignment pattern in the various layers of the substrate, or by depositing material with such alignment patterns. However, conventional manufacturing techniques tend to degrade the alignment features as processing proceeds from layer to layer. For example, a layer deposited in an alignment feature after a via fill step may tend to form patterns in and around the alignment feature to such a degree that the geometry of the alignment feature becomes difficult to see with the desired precision.
As the geometries of integrated circuits continues to shrink, the errors that are introduced by such alignment problems tend to have a greater effect on the performance of the integrated circuits. For example, with smaller structures created in the integrated circuits, an alignment shift of a tenth of a micron or so, which may have been acceptable in an integrated circuit with large features, is not tolerable in an integrated circuit with small features.
What is needed, therefore, is a system for more precisely aligning layers one to another.
The above and other needs are met by a method for forming an alignment feature on a substrate. The alignment feature is of the type concurrently formed with an electrically conductive layer overlying an electrically nonconductive layer having vias. The vias are filled with an electrically conductive material, and the alignment feature has a smaller aspect ratio than the vias. The alignment feature is not filled with the electrically conductive material when a first amount of the electrically conductive material, sufficient to just fill the vias, is deposited on the substrate. The first amount of the electrically conductive material within the alignment feature is not sufficient to prevent the alignment feature in the electrically conductive layer from distorting, and thereby reducing the effectiveness of the alignment feature.
The improvement is in depositing an additional amount of the electrically conductive material on the substrate. The additional amount is more than the first amount that is just sufficient to fill the vias, and fills the alignment feature to a level sufficient to prevent the alignment feature in the electrically conductive layer from distorting and reducing the effectiveness of the alignment feature.
In various preferred embodiments, the substrate is silicon, the electrically nonconductive layer is silicon oxide, the electrically conductive material is tungsten, and the electrically conductive layer is either aluminum or copper. According to another aspect of the invention there is provided an integrated circuit having an alignment feature formed according to the method described above.